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The basic function of the controller

The data buffer: the rate of I/O equipment, low CPU and memory is very high, therefore, must be set a buffer in the controller. In the output buffer, the buffer by high speed data transmitted, rate and then to I/O equipment has the buffer data to the I/O devices; in the input buffer is used for temporary storage, the data sent from I/O equipment, to be received by a number of data, then the data in the buffer high speed transmission to the host.

Error control: device controller is also in charge of error detection to data transmitted by I/O equipment. If you find the wrong delivery, usually the error detection code set, and report to CPU, then CPU will data the transmission to a void, and re transmit once. This will ensure the correctness of data input.

Data exchange: This refers to between CPU and controller, the controller and the equipment data exchange. For the former, is through the data bus, the CPU parallel to write the data controller, or from the controller in parallel readout data; for the latter, is a device to input data into the controller, or to the equipment from the controller transmits. Therefore, the controller must set the data register.

Status: state controller identifies and reports of equipment shall be recorded for CPU to understand the state of equipment. For example, only when the device is ready to send state, CPU can start controller reads the data from the device. Therefore, a status register should be set in the controller, using each one to reflect a state of equipment. When the CPU reads the contents of the register, to understand the status of equipment.

To receive and recognize the command: CPU to the controller sends a different command, equipment controller should be able to receive and recognize these commands. Therefore, the controller should have the corresponding control register, used to store the received commands and parameters, and decodes the received command. For example, the disk controller can receive the CPU to the Read, Write, Format and other 15 different orders, and some commands with parameters; correspondingly, a plurality of registers and a command decoder in a disk controller.

Address recognition: each unit as in memory has an address, each device in the system also have an address, and the equipment controller must be able to identify each device which is controlled by the address. In addition, in order to make CPU to (or from) the register write (or read) data, these registers should have a unique address.

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